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Cache-processor coupling: a fast and wide on-chip data cache design

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4 Author(s)
Motomura, M. ; Syst. ULSI Res. Lab., Microelectron. Res. Lab., Kanagawa, Japan ; Inoue, T. ; Yamada, H. ; Konagaya, A.

This paper presents a new data cache design, cache-processor coupling, which tightly binds an on-chip data cache with a microprocessor. Parallel architectures and high-speed circuit techniques are developed for speeding address handling process associated with accessing the data cache. The address handling time has been reduced by 51% by these architectures and circuit techniques. On the other hand, newly proposed instructions increase data cache bandwidth by eight times. Excessive power consumption due to the wide-bandwidth data transfer is carefully avoided by newly developed circuit techniques, which reduce dissipation power per bit to 1/26. Simulation study of the proposed architecture and circuit techniques yields a 1.8 ns delay each for address handling, cache access, and register access for a 16 kilobyte direct mapped cache with a 0.4 μm CMOS design rule

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:30 ,  Issue: 4 )

Date of Publication:

Apr 1995

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