By Topic

A single-chip Viterbi decoder for a binary convolutional code using an adaptive algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Wen-Ta Lee ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Ming-Hwa Chan ; Liang-Gee Chen ; Mao-Chao Lin

By using an adaptive algorithm, we design a single-chip Viterbi decoder for a rate 1/2 binary convolutional code. The adaptive algorithm is realized by threshold checking at each stage. The survivor paths that are less likely are ignored and hence the number of states at each decoding stage to be computed is reduced significantly in comparison with the conventional Viterbi decoder. Therefore, the decoding speed can be increased. A single-chip hard-decision decoder for a rate 1/2 convolutional code with constraint length K=6 (64 states) has been fabricated in 1.2 μm CMOS technology. Experimental results show that this improved algorithm can achieve a data throughput rate about 3 times faster than that using a conventional algorithm without sacrificing the decoding reliability

Published in:

Consumer Electronics, IEEE Transactions on  (Volume:41 ,  Issue: 1 )