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Top-down lower bounds for depth 3 circuits

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3 Author(s)
Hastad, J. ; Dept. of Comput. Sci., R. Inst. of Technol., Stockholm, Sweden ; Jukna, S. ; Pudlak, P.

We present a top-down lower bound method for depth 3 AND-OR-NOT circuits which is simpler than the previous methods and in some cases gives better lower bounds. In particular we prove that depth 3 AND-OR-NOT circuits that compute PARITY resp. MAJORITY require size at least 20.618...√n resp. 20.849...√n. This is the first simple proof of a strong lower bound by a top-down argument for non-monotone circuits

Published in:

Foundations of Computer Science, 1993. Proceedings., 34th Annual Symposium on

Date of Conference:

3-5 Nov 1993