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Cracking failures in lead-on-chip packages induced by chip backside contamination

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3 Author(s)
Amagai, M. ; Texas Instrum., Oita, Japan ; Seno, H. ; Ebe, K.

The increasingly severe demands of concurrently increasing die size while reducing package size have made the mechanical stability of novel surface mount technologies a primary concern. Package cracks induced by interfacial delamination between the chip backside surface and the epoxy molding resin are a major failure mode in Lead-On-Chip (LOC) packages. This interfacial delamination is caused by contamination of the backside surface by the wafer tape adhesive. The physical and chemical parameters of the backside surface and tape adhesive which lead to interfacial delaminations in LOC packages are described along with a method to alleviate the problem. To investigate which adhesive attributes impacted interfacial delamination, wafer tape adhesive samples were prepared with a variety of different base polymers, oligomers, cross-linking agents, photoinitiator, and additives. The degree and type of backside contamination left by these various adhesives was determined with scanning electron microscope (SEM) and scanning acoustic tomography (SAT) techniques. The adhesive and the chip backside surfaces were characterized with viscoelastic, particle count, wafer contact angle, and atomic force microscope (AFM) measurements

Published in:

Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, IEEE Transactions on  (Volume:18 ,  Issue: 1 )