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A 6 GHz 68 mW BiCMOS phase-locked loop

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2 Author(s)
Razavi, B. ; AT&T Bell Labs., Holmdel, NJ, USA ; Sung, J.J.

The design of a 6 GHz fully monolithic phase-locked loop fabricated in a 1 μm, 20 GHz BiCMOS technology is described. The circuit incorporates a voltage-controlled oscillator that senses and combines the transitions in a ring oscillator to achieve a period equal to two ECL gate delays. A mixer topology is also used that exhibits full symmetry with respect to its inputs and operates with supply voltages as low as 1.5 V. Dissipating 60 mW from a 2 V supply, the circuit has a tracking range of 300 MHz, an rms jitter of 3.1 ps, and phase noise of -75 dBc/Hz at 1 kHz offset

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:29 ,  Issue: 12 )

Date of Publication:

Dec 1994

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