Referenced Items are not available for this document.
The design of a 6 GHz fully monolithic phase-locked loop fabricated in a 1 μm, 20 GHz BiCMOS technology is described. The circuit incorporates a voltage-controlled oscillator that senses and combines the transitions in a ring oscillator to achieve a period equal to two ECL gate delays. A mixer topology is also used that exhibits full symmetry with respect to its inputs and operates with supply voltages as low as 1.5 V. Dissipating 60 mW from a 2 V supply, the circuit has a tracking range of 300 MHz, an rms jitter of 3.1 ps, and phase noise of -75 dBc/Hz at 1 kHz offset
Published in:
Solid-State Circuits, IEEE Journal of
(Volume:29
,
Issue:
12
)
Date of Publication: Dec 1994
- Page(s):
- 1560 - 1565
- ISSN :
- 0018-9200
- INSPEC Accession Number:
- 4854350
- Digital Object Identifier :
- 10.1109/4.340431
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Dec 1994
- Sponsored by :
- IEEE Solid-State Circuits Society
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