A 320 MHz CMOS triple 8 bit DAC with on-chip PLL and hardware cursor

A 320 MHz triple 8 bit DAC with on-chip phase-locked loop (PLL), hardware cursor function, and an architecture that relies on time-interleaved logic blocks is presented. Overall device performance is optimized by operating different portions of the circuit at different frequencies and combining parallelism with time-interleaving to minimize the hardware cost. Clock multiplication by the on-chip PLL improved the maximum frequency of operation of the prototype circuits by 20 percent. The PLL operates from 20-500 MHz and has a peak-to-peak jitter of 60 ps at an operating frequency of 432 MHz. The 10 mm/spl times/10 mm chip was fabricated in a 0.8 /spl mu/m CMOS process and dissipates 1.54 W from a single 5 V supply.<
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