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Distributed solutions to the delay fault test quality evaluation problem

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2 Author(s)
I. Pramanick ; POWER Parallel Syst., IBM Corp., Kingston, NY, USA ; A. K. Pramanick

Delay testing continues to gain importance as manufacturers try to meet stricter requirements for higher performance and higher density integrated circuits. The methodology to obtain a set of high quality gate delay fault detecting tests is unfortunately computationally intensive enough to be intractable for reasonably large VLSI circuits; parallelization of these computations is thus an attractive scenario. We present, for the first time, distributed algorithms for gate delay fault simulation and fault coverage determination through test quality evaluation. These algorithms are implemented over a network of workstations, which is normally available at most design labs, and thus do not rely os the use of very specialized, expensive, or difficult-to-access hardware. These algorithms are theoretically analyzed, and experimental studies of their implementation are reported. The results conform to the theoretically predicted performance, with speedups of up to 10 being obtained with 15 workstations

Published in:

High Performance Distributed Computing, 1994., Proceedings of the Third IEEE International Symposium on

Date of Conference:

2-5 Aug 1994