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Towards incorporating device parameter variations in timing analysis

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2 Author(s)
M. Sivaraman ; Carnegie Mellon Univ., Pittsburgh, PA, USA ; A. J. Satrojwas

Presents a timing verification mechanism which finds the maximum true delay of the circuit and the combination of the device parameter variations-caused by the imperfect fabrication process-which produces this worst-case. The effect of device parameter variations is captured to produce correlated component delay models. These delay models are then incorporated into an accurate analysis approach involving timed path sensitization expressions and device parameter space exploration to find the worst-case instance

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994