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Test of bridging faults in scan-based sequential circuits

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2 Author(s)
Isern, E. ; Dept. d''Enginyeria Electronica, Univ. Politecnica de Catalunya, Barcelona, Spain ; Figueras, J.

An IDDQ testing strategy combined with logical scan-out observation for bridging faults in scan-based sequential circuits is presented. Internal and external zero resistance bridging faults in both the combinational part and the scan path are considered. The testing strategy targets the faults beginning with those harder to detect. Thus, combinational internal shorts and combinational external shorts are targeted first. Remaining external shorts in the scan path are considered later. A standard ATPG for stuck-at faults, adapted to short fault detection, is used. In order to reduce the test application time, the time to apply IDDQ test vectors and the time to produce a shift in the scan chain is taken into account. Results of the experimentation on ISCAS'89 circuits show that the strategy provides high quality test sets of reduced size with the highest obtainable coverages for both internal and external shorts

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994