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Synthesis of system-level bus interfaces

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2 Author(s)
Narayan, S. ; Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA ; Gajski, D.D.

Given a set of communication channels to be implemented as a single bus, the authors present a bus-generation algorithm which determines the width of a bus implementation. Tradeoffs between the width of the bus and the performance of the processes communicating over the bus are evaluated. The algorithm incorporates system level constraints such as data transfer rates and the number of pins and allows several channels that may be transferring different sizes of data to be implemented as a single bus. The authors demonstrate through a detailed example the usefulness of the algorithm in implementing system-level interfaces between modules

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994