Cart (Loading....) | Create Account
Close category search window
 

Efficient path identification for delay testing - time and space optimization

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Wittman, H. ; Inst. of Electron. Design Autom., Tech. Univ. Munchen, Germany ; Henftling, M.

This paper presents an efficient method of handling a large number of paths during path-delay fault testing. Instead of handling the corresponding set of signals, an identifier is derived for every path. We handle up to three billion paths because the memory requirement is only about three bits per path. Compared to former approaches, experimental results show fast access, small memory requirements, and negligible CPU-times for the management of huge path sets

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.