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Efficient calculation of Boolean relations for multi-level logic optimization

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2 Author(s)
B. Wurth ; Inst. of Electron. Design Autom., Tech. Univ. Munich, Germany ; N. Wehn

A new exact technique is presented to calculate the maximal Boolean relation for an arbitrary subcircuit in a multi-level logic circuit. The new technique significantly reduces the memory required for BDD-based Boolean relation calculation. It therefore permits the calculation of Boolean relations for much more complex circuits than was previously possible. The efficiency of the technique is demonstrated on various benchmark circuits. An application to multi-level logic optimization is shown

Published in:

European Design and Test Conference, 1994. EDAC, The European Conference on Design Automation. ETC European Test Conference. EUROASIC, The European Event in ASIC Design, Proceedings.

Date of Conference:

28 Feb-3 Mar 1994