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Hierarchical reconfiguration of VLSI/WSI arrays

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3 Author(s)
Bhatia, D. ; Dept. of Electr. & Comput. Eng., Cincinnati Univ., OH, USA ; Rajagopalan, R. ; Katkoori, S.

We present a reconfiguration algorithm for yield enhancement of VLSI/WSI arrays. Our algorithm, is based on row/column elimination. We introduce the notion of element-bypass and use it to eliminate partial row(s) and partial column(s). In doing so we enhance the harvest greatly. Experimentally we are able to attain harvest which is many folds better than that reported in comparable studies. Our method has no hardware overhead and compares well with other methods that have substantial hardware overhead

Published in:

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Date of Conference:

5-8 Jan 1994