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An improved deductive fault simulator

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4 Author(s)
P. R. Sureshkumar ; Hindustan Aeronaut. Ltd., Bangalore, India ; J. Jacob ; M. K. Srinivas ; V. D. Agrawal

We propose several improvements to the well known deductive fault simulation algorithm. First, sensitivity analysis is used during true value simulation to classify each gate of the circuit into one of the two classes, namely, definitely sensitive (DS) or potentially sensitive (PS). For these classes, simple rules are given to compute the output fault list from the input fault lists. Further, the basic operations of set union, set intersection and set difference, used in fault list computation, are made highly efficient by novel pointer referencing on implicitly ordered fault lists. Performance enhancements over the basic deductive fault simulation algorithm are demonstrated by experimental results on ISCAS-85 combinational benchmark circuits. Experimental results on ISCAS-89 sequential benchmarks show that our improvements make the simulator faster than a highly efficient concurrent fault simulator, Hysim-3

Published in:

VLSI Design, 1994., Proceedings of the Seventh International Conference on

Date of Conference:

5-8 Jan 1994