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On minimizing hardware overhead for pseudoexhaustive circuit testability

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3 Author(s)
D. Kagaris ; Comput. Sci. Program, Dartmouth Coll., Hanover, NH, USA ; F. Makedon ; S. Tragoudas

A self-contained method with very low bypass storage cell (BSC) overhead is presented. The method uses a graph model to represent the circuit under test. This unifying model makes the method applicable to both the gate level and the module level. A non-necessarily-partitioning technique reduces the number of BSCs considerably

Published in:

Computer Design: VLSI in Computers and Processors, 1992. ICCD '92. Proceedings, IEEE 1992 International Conference on

Date of Conference:

11-14 Oct 1992