Cart (Loading....) | Create Account
Close category search window
 

Verification of digital circuits based on formal semantics of a hardware description language

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Mutz, M. ; Passau Univ., Germany

The author presents basic concepts of defining semantics of the hardware description language VIOLA based on higher-order logic (HOL). The verification procedures of the hardware verification system VERENA are based on transformations of VIOLA terms. The correctness of these transformation steps can be formally verified based on the HOL semantics of the related VIOLA terms. As a mechanical tool, the HOL prove assistant is used. Basic concepts of a special verification system for the formal verification of digital circuits are presented. HOL serves as the formalism to define the underlying theory

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.