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Heuristics for branch-and-bound global attraction

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5 Author(s)
J. Septien ; Dept. de Inf. & Autom., Univ. Complutense de Madrid, Spain ; D. Mozos ; F. Tirado ; R. Hermida
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A set of heuristics designed to guide the behavior of a global branch-and-bound hardware allocator is described. An area estimation heuristic, including interconnection area, is used as a cost function to be minimized. A design space bounding heuristic allows pruning the design space in a more intelligent way than any other system. Design space search guiding heuristics are incorporated so that reordering the available alternative leads first to the most interesting regions of the design space. This accelerates the solution search, leading more quickly to the best designs

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992