Referenced Items are not available for this document.
The authors present two methods for optimizing the topology of given power/ground networks on VLSI chips. The cycle-reduction-method removes cycles and root paths (paths between two pads) in a general power/ground graph. The node-reduction-method removes branching nodes (nodes incident to more than two branches) in a power/ground tree. Both methods yield a reduction of the power/ground routing area and do not degrade the reliability of the power/ground network. Small examples to explain the procedures are included and experimental results for benchmark circuits are presented
Published in:
Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European
Date of Conference: 7-10 Sep 1992
- Page(s):
- 362 - 367
- Meeting Date :
- 07 Sep 1992-10 Sep 1992
- Print ISBN:
- 0-8186-2780-8
- INSPEC Accession Number:
- 4493541
- Conference Location :
- Hamburg
- Digital Object Identifier :
- 10.1109/EURDAC.1992.246218
- Product Type:
- Conference Publications
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