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Using VHDL for datapath synthesis

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4 Author(s)
V. Olive ; Rance-Telecom, CNET-Grenoble, Meylan, France ; R. Airiau ; J. M. Berge ; A. Robert

The authors present a VHSIC hardware description language (VHDL) interface for a datapath generator. It introduces a method which is specific as well as library management for simulating and making synthesis. Implementing the data-path layout is discussed, and the specific use of VHDL for building the circuit layout is described. The entire interface has been specified in VHDL, demonstrating the possibility of extending the semantics of VHDL by adding particular attributes

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992