By Topic

Evaluation criteria of HDLs: VHDL compared to Verilog, UDL/I and M

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Maginot, S. ; LEDA SA, Meylan, France

VHSIC hardware description language (VHDL) is compared to three other well-known hardware description languages: Verilog (from Cadence Design Systems, now public), UDL/1 (new Japanese standards,) and M (from Mentor Graphics). This comparative study parallels the fundamental concepts of these languages and highlights the different design processes and methodologies they require. VHDL is a general-purpose modeling language, whereas Verilog, UDL/I and M are more dedicated to IC modeling. The predefined environment of VHDL compares poorly to the implicit IC environment of other languages

Published in:

Design Automation Conference, 1992., EURO-VHDL '92, EURO-DAC '92. European

Date of Conference:

7-10 Sep 1992