Referenced Items are not available for this document.
The design of a monolithic phase-locked loop (PLL) used in a gigabit serial data link interface for clock and data extraction is described. Implemented in a triple-metal 25-GHz f/sub t/ bipolar process and consuming 85 mA from a 5 V-supply, the PLL has a wide frequency acquisition range, from 600 MHz to 1.5 GHz, and a recovered clock phase jitter of less than 18.3 ps r.m.s. The PLL requires only one external component (the loop filter capacitor) needs no adjustment, and is suitable for large-scale integration.<
Published in:
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Date of Conference: 4-6 June 1992
- Page(s):
- 70 - 71
- Meeting Date :
- 04 Jun 1992-06 Jun 1992
- Print ISBN:
- 0-7803-0701-1
- INSPEC Accession Number:
- 4437406
- Conference Location :
- Seattle, WA, USA
- Digital Object Identifier :
- 10.1109/VLSIC.1992.229282
- Product Type:
- Conference Publications
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