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500 Mbyte/sec data-rate 512 Kbits*9 DRAM using a novel I/O interface

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14 Author(s)
Kushiyama, N. ; Toshiba Corp., Kawasaki, Japan ; Ohshima, S. ; Stark, D. ; Sakurai, K.
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A novel 512-kb*9 DRAM with a 500-Mbyte/s data transfer rate has been designed. This high data-rate has been achieved by coupling a very high internal column bandwidth DRAM core with a very high internal column bandwidth, and coupling this core with a block oriented, small-swing, synchronous interface that uses skew canceling clocks. The DRAM has a 1-kbyte*2 line sense amplifier cache. This DRAM is assembled in a 32-pin vertical surface mount type plastic package.<>

Published in:

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Date of Conference:

4-6 June 1992