A high-speed parallel pipelined ADC technique in CMOS

A new architecture consisting of a time-interleaved array of pipelined A/D converters (ADCs) is presented. A prototype has been designed consisting of four switched-capacitor (S/C) multistage pipelined ADCs in parallel. Digital error correction is employed to ease comparator accuracy requirements. A key circuit issue is the design of a high-speed sample-and-hold (S/H) amplifier. A fully differential, mostly NMOS, unfolded cascode operational amplifier topology is used. Results from an experimental chip implemented in 1 mu m CMOS are presented.<
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