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A low power 12 b analog-to-digital converter with on-chip precision trimming

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3 Author(s)
M. deWit ; Texas Instrum., Dallas, TX, USA ; K. S. Tan ; R. K. Hester

The design and performance of a 12 b charge redistribution ADC is described. The architecture is chosen to minimize conversion time and power dissipation. Die area is minimized by a modified self-calibration algorithm and nonvolatile memory based on polysilicon fuses. The ADC is fabricated in a linear 1 mu m CMOS process. The die area, including the 12 b parallel digital interface is 15 kmil/sup 2/. The power dissipation is under 15 mW, making the energy per conversion only 45 nJ.<>

Published in:

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Date of Conference:

4-6 June 1992