Referenced Items are not available for this document.
The authors describe the multitiming buffering architecture (MTBA) and the pseudo hierarchical word decoding architecture (pseudo-HWD). These architectures have been implemented on a 4M emitter-coupled logic (ECL) SRAM with a 0.6- mu m BiCMOS process, and have effectively reduced the peak current of the decoding circuit by 32% and maximum di/dt by 63%, as compared with the three-level HWD. The SRAM achieved a 7-ns access time and a 160-mA active current at 50 MHz.<
Published in:
VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on
Date of Conference: 4-6 June 1992
- Page(s):
- 30 - 31
- Meeting Date :
- 04 Jun 1992-06 Jun 1992
- Print ISBN:
- 0-7803-0701-1
- INSPEC Accession Number:
- 4427057
- Conference Location :
- Seattle, WA, USA
- Digital Object Identifier :
- 10.1109/VLSIC.1992.229251
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