By Topic

Circuit techniques for multi-bit parallel testing of 64 Mb DRAMs and beyond

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
T. Sakuta ; Hitachi Ltd., Tokyo, Japan ; M. Muranaka ; H. Matsuura ; H. Tanaka
more authors

Through the use of a high-speed compression circuit that can compress data signals of low amplitude, high-speed 32-b parallel processing tests for 64 MDRAMs have been achieved. Through the use of a low-power dynamic-type differential amplifier, highly compressed 128-b parallel processing tests have been made possible. By including appropriate test circuits based on independent concepts corresponding to the testing of the peripheral circuits and that of the memory cell, the testing function of 64 MDRAMs has become practical. Design features and characteristics of the 64 MDRAM are summarized.<>

Published in:

VLSI Circuits, 1992. Digest of Technical Papers., 1992 Symposium on

Date of Conference:

4-6 June 1992