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Residue arithmetic based multiple-valued VLSI image processor

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3 Author(s)
Honda, M. ; Tohoku Univ., Sendai, Japan ; Kameyama, M. ; Higuchi, T.

An ultra-high-performance VLSI image processor based on a multivalued residue arithmetic circuit is proposed for robot vision. Data communication between the mod mi arithmetic units is not necessary in the residue arithmetic system, so that multiple mod mi arithmetic units can be on different chips. Therefore, a number of mod mi multiplier adders can be implemented on a single VLSI chip based on the modulus-slice concept. Each mod mi arithmetic unit can be effectively implemented in parallel using the concept of pseudoprimitive root and multivalued current-mode circuit technology. Thus, the use of parallelism throughout makes the performance very high in comparison with the ordinary binary implementation

Published in:

Multiple-Valued Logic, 1992. Proceedings., Twenty-Second International Symposium on

Date of Conference:

27-29 May 1992