The characteristics of the successful m-valued I 2L and ROMs that have been designed in the past are examined, and the reasons for their success are discussed. The problems associated with scaling of m-valued CMOS current mode circuits are examined. The tolerance issue, the respective propagation delays of binary and m-valued ICs, and the interconnection issue are considered. The challenges for m-valued circuits in competition with the exponential performance increase of binary circuits are identified
Published in:
Multiple-Valued Logic, 1992. Proceedings., Twenty-Second International Symposium on
Date of Conference:
27-29 May 1992
- Page(s):
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156
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164
- Meeting Date :
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27 May 1992-29 May 1992
- Print ISBN:
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0-8186-2680-1
- INSPEC Accession Number:
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4303545
- Conference Location :
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Sendai
- Digital Object Identifier :
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10.1109/ISMVL.1992.186790
- Product Type:
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Conference Publications