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A new balanced gate for structural testing

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2 Author(s)
Razavi, H.M. ; North Carolina Univ., Charlotte, NC, USA ; Wong, P.W.

A new circuit realization is presented for a family of gates that results in a simple test for structural integrity of a CMOS circuit. The gate during normal operation behaves like an ordinary CMOS gate. However, in the test mode a nominal voltage of 2.5 V on the inputs of the gate would result in a 2.5-V output if no stuck-at faults are present. A combinational circuit designed exclusively with this type of a gate can be tested for all stuck-at faults using a single test vector of 2.5 V on all primary inputs. It is shown that a 100% fault coverage is obtained at the gate level (90% at the transistor level) for a combinational circuit regardless of its size, function, and complexity

Published in:

Multiple-Valued Logic, 1992. Proceedings., Twenty-Second International Symposium on

Date of Conference:

27-29 May 1992