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Integration of algorithmic VLSI synthesis with testability incorporation

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2 Author(s)
Gebotys, C.H. ; Dept. of Electr. Eng., Waterloo Univ., Ont., Canada ; Elmasry, M.I.

A VLSI design synthesis approach with testability, area, and delay constraints is presented. This research differs from other synthesizers by implementing testability as part of the VLSI design solution. A binary-tree data structure is used throughout the testable design search. Its bottom-up and top-down algorithms provide data-path allocation, constraint estimation, and feedback for design exploration. The partitioning and two-dimensional characteristics of the binary-tree structure provide VLSI design floorplans and global information for test incorporation. A differential equation and elliptical wave filter example were used to illustrate the design synthesis with testability constraints methodology. Test methodologies such as multiple-chain scan paths and BIST (built-in self-test) with different test schedules were explored. Design scores comprised of area, delay, fault coverage, and test time were computed and graphed.<>

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:24 ,  Issue: 2 )