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Integrated pin electronics for VLSI functional testers

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2 Author(s)
Gasbarro, J.A. ; Xerox Palo Alto Res. Center, CA, USA ; Horowitz, M.A.

A fully integrated approach is presented for building the pin electronics portion of a VLSI functional tester. The system implements the output vector timing and formatting functions, as well as the input sampling and comparison operations. A computer-controlled feedback loop is employed to obtain a timing accuracy of better than 1 ns. Novel circuit designs are shown which make the circuit suitable for fabrication in a high-density MOS technology. An experimental chip using these techniques was fabricated in 2- mu m CMOS technology and functioned at over 30 megavectors per second.<>

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:24 ,  Issue: 2 )

Date of Publication:

April 1989

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