Referenced Items are not available for this document.
The application of a novel planarization process using a sacrificial fill layer of photoresist is presented. The process is shown to solve the planarization problems encountered in both intermetal dielectric for a 1.2 mu m 256 K SRAM technology and trench isolation for a0.8- mu m 1M SRAM technology. The process is a simple extension of the standard dielectric etch-back scheme. A discussion of how to precisely quantify circuit planarization using well-known techniques is also presented. This information can then be adapted for statistical quality control purposes.<
Published in:
Semiconductor Manufacturing, IEEE Transactions on
(Volume:1
,
Issue:
4
)
Date of Publication: Nov. 1988
- Page(s):
- 140 - 146
- ISSN :
- 0894-6507
- INSPEC Accession Number:
- 3312916
- Digital Object Identifier :
- 10.1109/66.17987
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Nov. 1988
- Sponsored by :
- IEEE Components, Packaging and Manufacturing Technology Society
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