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A 14-bit 20-MS/s Pipelined ADC With Digital Distortion Calibration

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4 Author(s)
Daito, M. ; Adv. Technol. Dev. Labs., Sharp Corp., Nara ; Matsui, H. ; Ueda, M. ; Iizuka, K.

A new digital distortion calibration technique is demonstrated in a 14-bit 20-MS/s pipelined analog-to-digital converter (ADC). Calibration parameters are obtained in a way similar to conventional digital gain calibration. The prototype ADC has been fabricated in a 0.18-mum CMOS process and consumes 33.7 mW at 2.8 V. Using the proposed calibration method, a 15-dB improvement of the third-order harmonic rejection is achieved. The measured SNDR and SFDR are 71.6 and 82.3 dB, respectively

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 11 )

Date of Publication:

Nov. 2006

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