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SRAM Circuit With Expanded Operating Margin and Reduced Stand-By Leakage Current Using Thin-BOX FD-SOI Transistors

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3 Author(s)
M. Yamaoka ; Central Res. Lab., Hitachi Ltd., Tokyo ; R. Tsuchiya ; T. Kawahara

The deterioration of operating margin and increasing leakage current in SRAM are becoming critical problems with the advance of process scaling. To solve these problems, we propose a low-power SRAM circuit using thin buried-oxide fully depleted silicon-on-insulator transistors. The back-gate bias is introduced to the SRAM circuits and acquires high operating margin and high-speed operation under low supply voltage. The leakage current in stand-by state is reduced. This SRAM achieves 30% faster writing time under low-voltage operation and 90% less stand-by power

Published in:

IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 11 )