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A Digital CMOS PWCL With Fixed-Delay Rising Edge and Digital Stability Control

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3 Author(s)
Young-Chan Jang ; Dept. of Electr. & Comput. Eng, Pohang Inst. of Sci. & Technol. ; Seung-Jun Bae ; Hong-June Park

A digital pulsewidth control loop (PWCL) with a fixed-delay rising edge and digital stability control is proposed for multiphase clock applications. In the duty-cycle tracking mode, the linear range of the input duty cycle was measured to be 28%-70%, with a maximum linearity deviation of 0.5%. In the duty-cycle correction mode, the correction range of the input duty cycle was measured to be 25%-75%, with the output duty cycle within 50 plusmn 0.4%. The chip was fabricated by using a 0.25-mum CMOS process with a 2.5-V supply. The chip area and the power consumption were 200 mumtimes250 mum and 18 mW at an input clock frequency of 1.0 GHz, respectively

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:53 ,  Issue: 10 )

Date of Publication:

Oct. 2006

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