CMOS Transconductors With Nearly Constant Input Ranges Over Wide Tuning Intervals

Three different bias strategies aimed to reduce the effect of tuning on either the differential input range or the common-mode range of triode-region CMOS transconductors are presented. The method is applied to an original transconductor topology that is optimized to produce ultralow G
_m
values. A prototype circuit, which was designed with the 0.35-mum bipolar-CMOS-DMOS (BCD6) process of STMicroelectronics, is presented. The effectiveness and limitations of the method are characterized by means of electrical simulations