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A Framework for Automatic Design Validation of RTL Circuits Using ATPG and Observability-Enhanced Tag Coverage

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3 Author(s)
L. Zhang ; Cadence Design Syst. Inc., San Jose, CA ; I. Ghosh ; M. S. Hsiao

This paper presents a framework for high-level design validation using an efficient register-transfer level (RTL) automatic test pattern generator (ATPG). The RTL ATPG algorithm first generates a test environment for each validation objective, which includes variable assignments, conditional statements, and arithmetic expressions in the hardware description language (HDL) description. The test environment for a given validation objective is a set of symbolic conditions that allow for full controllability and observability of that objective. After the RTL ATPG terminates, a back-end translator intelligently translates the test environments into validation vectors by filling in the necessary values. Since the observability of error effect is naturally handled by the RTL ATPG algorithm, this approach is superior to most existing validation methods, which only focus on the excitation of HDL constructs. A set of heuristics is proposed to utilize high-level circuit information to enhance the RTL ATPG algorithm and to maximize the validation efficiency. The RTL ATPG algorithm is also coupled with an improved RTL validation-coverage metric, which can help users to gain a higher degree of confidence on the quality of generated validation vectors. The usage of the coverage metric also results in the generation of compact vector sets. Experimental results on academic and industrial benchmark circuits demonstrate that our method is able to obtain very high design-error coverage in short execution times

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:25 ,  Issue: 11 )