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A Digital PLL with a Stochastic Time-to-Digital Converter

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5 Author(s)
Kratyuk, V. ; Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR ; Hanumolu, P.K. ; Ok, K. ; Mayaram, K.
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A new dual-loop digital PLL (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high frequency delta-sigma dithering to achieve a wide PLL bandwidth and low jitter at the same time. The test chip has been fabricated in a 0.13mum CMOS process. The DPLL features a 0.7-1.7 GHz oscillator tuning range, 6.9ps rms jitter and consumes 17mW while operating at 1.2GHz

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VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

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