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Wordline & Bitline Pulsing Schemes for Improving SRAM Cell Stability in Low-Vcc 65nm CMOS Designs

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9 Author(s)
Khellah, M. ; Circuits Res. Labs., Intel, Hillsboro, OR ; Yibin Ye ; Nam Sung Kim ; Somasekhar, D.
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Pulsed wordline (PWL) & pulsed bitline (PBL) techniques to improve SRAM cell stabilities in single-Vcc microprocessor designs are evaluated in 65nm CMOS. At 0.7V Vcc, PWL improves cell failure rate by 15times while incurring <1% area overhead. Both PBL & PWL with read-modify-write (PWL-RMW) provide the best improvements (26times) in cell stability, with significant area overheads (4-8%)

Published in:
VLSI Circuits, 2006. Digest of Technical Papers. 2006 Symposium on

Date of Conference: 0-0 0

Page(s):
9 - 10
Print ISBN:
1-4244-0006-6
INSPEC Accession Number:
9165508
Conference Location :
Honolulu, HI
Digital Object Identifier :
10.1109/VLSIC.2006.1705286
Product Type:
Conference Publications

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