Referenced Items are not available for this document.
This paper presents a 372 ps 64-bit adder using fast pull-up logic (FPL) in 0.18 mum CMOS technology. Fast pull-up logic is devised and applied to decrease pull-up time which is critical in domino-static adder. The implemented adder measures the worst case delay of 372 ps. The adder has a modified tree architecture using load distribution method and has 6 logic stages
Published in:
Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on
Date of Conference: 21-24 May 2006
- Page(s):
- 4 pp. - 16
- Print ISBN:
- 0-7803-9389-9
- INSPEC Accession Number:
- 9086537
- Conference Location :
- Island of Kos
- Digital Object Identifier :
- 10.1109/ISCAS.2006.1692510
- Product Type:
- Conference Publications
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