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Hierarchical bottom-up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard

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5 Author(s)
T. Eeckelaert ; Katholieke Universiteit Leuven, Belgium ; R. Schoofs ; G. Gielen ; M. Steyaert
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This paper describes key points and experimental validation in the development of a bottom-up hierarchical, multi-objective evolutionary design methodology for analog blocks. The methodology is applied to a continuous-time DeltaSigma A/D converter for WLAN applications, to generate a set of Pareto-optimal design solutions. The generated performance tradeoff offers the designer access to a set of optimal design solutions, from which the designer can choose a satisfactory design point according to the performance specifications. The presented method takes advantage of the Pareto-optimal performance solutions of the hierarchical lower-level sub-blocks to generate the overall Pareto-optimal set at system level. The way the lower-level performance tradeoffs are combined and propagated to higher hierarchical levels, is one of the major key points in the bottom-up methodology. The experimental results validate the methodology for a 7-block hierarchical decomposition of a complex high-speed Delta;Sigma A/D modulator for a WLAN 802.11a/b/g standard

Published in:

2006 43rd ACM/IEEE Design Automation Conference

Date of Conference:

24-28 July 2006