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A reconfigurable design-for-debug infrastructure for SoCs

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6 Author(s)
M. Abramovici ; DAFCA, Inc., Framingham, MA, USA ; P. Bradley ; K. Dwarakanath ; P. Levin
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In this paper we present a design-for-debug (DFD) reconfigurable infrastructure for SoCs to support at-speed in-system functional debug. A distributed reconfigurable fabric inserted at RTL provides a debug platform that can be configured and operated post-silicon via the JTAG port. The platform can be repeatedly reused to configure many debug structures such as assertions checkers, transaction identifiers, triggers, and event counters

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2006 43rd ACM/IEEE Design Automation Conference

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