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Dynamic state-retention flip-flop for fine-grained power gating with small design and power overhead

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7 Author(s)
Henzler, S. ; Infineon Technol. AG, Munich-Neubiberg ; Georgakos, G. ; Eireiner, M. ; Nirschl, T.
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Fine-grained power gating is the rigorous application of sleep transistor scheme to reduce stand-by power consumption in idle circuit blocks. Small circuit blocks are suspended for a short time while they are temporarily not needed. A sense-amplifier-based state retention flip-flop is proposed, that preserves the logical state of the circuit during these short idle periods. This dynamic state retention flip-flop requires neither additional control signals nor an additional power supply for its state retention functionality. An integration into a standard design flow is possible without any modifications. The tradeoff between propagation delay and retention time is derived analytically. Retention times in the range of milliseconds can be achieved with D-to-Q delays of 100 ps to 200 ps

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 7 )