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A high-speed 850-nm optical receiver front-end in 0.18-/spl mu/m CMOS

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2 Author(s)
C. Hermans ; ESAT-MICAS Lab., Katholieke Univ., Leuven, Belgium ; M. S. J. Steyaert

A high-speed optical interface circuit for 850-nm optical communication is presented. Photodetector, transimpedance amplifier (TIA), and post-amplifier are integrated in a standard 0.18-mum 1.8-V CMOS technology. To eliminate the slow substrate carriers, a differential n-well diode topology is used. Device simulations clarify the speed advantage of the proposed diode topology compared to other topologies, but also demonstrate the speed-responsivity tradeoff. Due to the lower responsivity, a very sensitive transimpedance amplifier is needed. At 500 Mb/s, an input power of -8 dBm is sufficient to have a bit error rate of 3middot10-10. Next, the design of a broadband post-amplifier is discussed. The small-signal frequency dependent gain of the traditional and modified Cherry-Hooper stage is analyzed. To achieve broadband operation in the output buffer, so-called "fT doublers" are used. For a differential 10 mVpp 231-1 pseudo random bit sequence, a bit error rate of 5middot10-12 at 3.5 Gb/s has been measured. At lower bit-rates, the bit error rate is even lower: a 1-Gb/s 10-mVpp input signal results in a bit error rate of 7middot10-14. The TIA consumes 17mW, while the post-amplifier circuit consumes 34 mW

Published in:

IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 7 )