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High-voltage power delivery through charge recycling

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4 Author(s)
Rajapandian, S. ; Dept. of Electr. Eng., Columbia Univ., New York, NY, USA ; Shepard, Kenneth L. ; Hazucha, P. ; Karnik, T.

In this paper, we describe a technique for delivering power to a digital integrated circuit at high voltages, reducing current demands and easing requirements on power-ground network impedances. The design approach consists of stacking CMOS logic domains to operate from a voltage supply that is a multiple of the nominal supply voltage. DC-DC downconversion is performed using charge recycling without the need for explicit downconverters. Experimental results are presented for the prototype system in a 0.18-μm CMOS technology operating at both 3.6 V and 5.4 V. Peak energy efficiencies as high as 93% are demonstrated at 3.6 V.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:41 ,  Issue: 6 )