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A 155.52 mbps-3.125 gbps continuous-rate clock and data recovery circuit

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5 Author(s)
Rong-Jyi Yang ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Kuan-Hua Chao ; Sy-Chyuan Hwu ; Chuan-Kang Liang
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A 155.52 Mbps-3.125 Gbps continuous-rate clock and data recovery (CDR) circuit using the full-rate bang-bang phase detector is presented. A frequency detector is proposed to eliminate the harmonic locking problem even with a wide range of data rates and its theoretical analysis is also discussed. A quadrature divider is also presented to generate the clocks with accurate quadrature phases. This CDR circuit has been realized in a 0.18-μm CMOS process and its die area is 1.1×0.8 mm2. It consumes 95 mW at the highest bit rate of 3.125 Gbps. It can recover the NRZ data of a 231-1 PRBS with the bit rate ranging from 155.52 Mbps to 3.125Gbps for the incremental frequency acquisition and the NRZ data of a 27-1 PRBS for the decremental frequency acquisition. All the measured bit error rates are less than 10-12.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:41 ,  Issue: 6 )