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A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors

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32 Author(s)
Jan, C.-H. ; Logic Technol. Dev., Intel Corp., Hillsboro, OR ; Bai, P. ; Choi, J. ; Curello, G.
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A leading edge 65nm logic process technology employing uni-axial strained silicon transistors has been optimized for ultra low power products. Record PMOS/NMOS drive currents of 0.38/0.66 mA/mum, respectively, have been achieved at 1.2V and off-state leakage of 100 pA/mum. Greater than 1000times reduction of SRAM cell standby leakage through implementation of sleep transistors and other leakage suppression schemes are also discussed

Published in:

Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International

Date of Conference:

5-5 Dec. 2005