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On-chip debugging-based fault emulation for robustness evaluation of embedded software components

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4 Author(s)
Ruiz, J.-C. ; Fault-Tolerant Syst. Group, Valencia Tech. Univ., Spain ; Pardo, J. ; Campelo, J.-C. ; Gil, P.

As manufacturers integrate more off-the-shelf components in embedded products, their robustness evaluation becomes more necessary. This requirement is however difficult to meet using non-intrusive evaluation methods, especially in the case of systems-on-a-chip (SoCs). Research presented in this paper investigates the use of on-chip-debugging (OCD) mechanisms to evaluate the ability of SoC-embedded software components to withstand the occurrence of external faults. These faults are emulated by corrupting the information that components are able to receive through their public interfaces. Once a fault has been injected, reaction of targeted components is studied using OCD monitoring capabilities. The ability of these capabilities to run in parallel with the rest of the SoC internal mechanisms is exploited in order to carry out previous tasks without requiring the source code of the component under study and without interfering (neither spatially nor temporally) with the system nominal execution. Results show potentials and limitations of the approach and let us define directions for future investigation.

Published in:

Dependable Computing, 2005. Proceedings. 11th Pacific Rim International Symposium on

Date of Conference:

12-14 Dec. 2005

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