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A low-power correlation-derivative CMOS VLSI circuit for bearing estimation

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3 Author(s)
P. Julian ; Electr. & Comput. Eng. Dept., Johns Hopkins Univ., Baltimore, MD, USA ; A. G. Andreou ; D. H. Goldberg

We present a CMOS integrated circuit (IC) for bearing estimation in the low-audio range that performs a correlation derivative approach in a 0.35-/spl mu/m technology. The IC calculates the bearing angle of a sound source with a mean variance of one degree in a 360/spl deg/ range using four microphones: one pair is used to produce the indication and the other to define the quadrant. An adaptive algorithm decides which pair to use depending on the direction of the incoming signal, in such a way to obtain the best estimate. The IC contains two blocks with 104 stages each. Every stage has a delay unit, a block to reduce the clock speed, and a 10-bit UP/DN counter. The IC measures 2 mm by 2.4 mm, and dissipates 600 /spl mu/W at 3.3 V and 200 kHz. It is purely digital and uses a one-bit quantization of the input signals.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:14 ,  Issue: 2 )