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Layout-driven architecture synthesis for high-speed digital filters

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4 Author(s)
Dongku Kang ; Electr. & Comput. Eng. Dept., Purdue Univ., West Lafayette, IN, USA ; H. Choo ; K. Muhammad ; K. Roy

We propose a floorplan-aware complexity reduction methodology for digital filters. Conventional methodologies for complexity reduction use logic-centric approaches focusing on the total number of adders. Therefore, there is a need to consider interconnects to reduce communication costs while synthesizing reduced-complexity filters. In this paper, we integrate high-level synthesis and floorplan to obtain improvement in both computational complexity and interconnect delay. In our experiments, we could achieve 15% improvement in critical-path delay over conventional methodologies.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:14 ,  Issue: 2 )